Our HVS (Hybrid Vision Sensor) technology, employs a pixel-level event-image hybrid design that integrates both image sampling and event detection circuits within the same pixel array. Leveraging in-pixel sensing-storage-computation integration, architectures such as iampCOMB, GESP, or IN-PULSE DiADC, and a time interleaving technology readout mechanism (PixMU), the sensor supports optional output in image mode, event mode, or hybrid vision mode—balancing full-image integrity with dynamic response capability. Using BSI (back-side-illumination) stacking and advanced inter-pixel isolation technology, it achieves both pixel miniaturization and high photoelectric performance. HVS’s data path is compatible with MIPI and supports algorithm stacks based on ISP/NPU/DVP/QSPI/LVDS.